Redwood
Redwood: A Frontier AI Accelerator Designed, Verified, and Deployed from Scratch in 2 Weeks by AIArchitect Labs reports an AI system that took a high-level specification from two human architects and generated the performance model, RTL, UVM test environments, formal proofs, firmware and kernels for a low-latency inference accelerator in under two weeks. Its FPGA variant, Redwood Nano, runs multi-billion-parameter models such as Llama and Qwen.
An AI design system writes and verifies the hardware and software of an AI accelerator, and a model deployed on that accelerator is then used to improve the next generation. The company reports that Qwen running on Redwood, exposed as an API endpoint, found timing and kernel optimizations for the accelerator itself, which it calls an early step toward recursive self-improvement.
- AI system writes accelerator hardware
- Qwen runs on the new accelerator
- Qwen finds optimizations for the accelerator
- Optimizations improve next accelerator generation
- AI system writes accelerator hardware
- Qwen runs on the new accelerator
- Qwen finds optimizations for the accelerator
- Optimizations improve next accelerator generation
Why it is a road to recursion
It reports one full turn of the hardware loop: AI designed a chip, a model ran on that chip, and that model contributed to the next chip's design.
Evidence
Projected onto Samsung 8 nm, the company reports 1.75x the throughput of a measured Jetson Orin Nano baseline at 1.9x lower power (3.4x performance per watt); these are projections, as the design currently runs on an FPGA.
Related loops
More hardware and chips →- RL agent lays out TPU blocks
- Better layouts make AI hardware cheaper
- Agent pre-trains on earlier chip generations
- repeat
- AI systems would design chips
- Chips would train more capable AI
- That AI designs the next chips
- repeat